Sanghoon Kwak
Post-doctoral Researcher at System Synthesis Lab., School of EECE, Seoul National University
Seoul, Republic of Korea
Research Interests
Asynchronous Circuit
n Logic & high-level synthesis of asynchronous circuit
CAD Algorithm
n Logic & behavioral synthesis technique, technology mapping
Embedded System
n Network-On-Chip architecture, MPSoC (Multi-Processor System-on-Chip) Design
n H/W-S/W Co-Design of Embedded System
Contact Points
- shkwak AT ssl.snu.ac.kr or kwak.sanghoon AT gmail.com
Education
- PhD in Dept. of Info. & Comm., Gwangju Institute of Science and Technology (GIST) : 2000.3 – 2009.2
- MS in Dept of Info. & Comm., Gwangju Institute of Science and Technology (GIST) : 1998.3 – 2001.2
- BS in Dept. of Computer Engineering, Computer Engineering, Dongguk University : 1991.3 – 1998.2
Work Experiences
2009. 8– Current : Postdoctoral Researcher at System Synthesis Lab., Schol of EECE, Seoul National University (Advisor : Prof. Taewhan Kim)
2009. 3– 2009.8 : Postdoctoral Researcher at Communication System Lab., Dept. of Info. & Comm.,GIST
2000. 3 – 2001. 2 : Part -time Researcher in SDA (System Design Automation) Team, ETRI
- Developed SDL2C Translator for H/W-S/W Co-Design Environment
Project Experiences
n Analysis of Open Source CAD Tool (BALSA) for Asynchronous Circuit Synthesis, funded by ETRI (Electronics and Telecommunication Research Institute in Korea), 2007. 7 – 2007. 11
- BALSA is a popular public-domain asynchronous CAD tool. In this project, we focused on modification of BALSA back-end flow to adopt a new commercial process technology. By the modification of BALSA back-end, a DI(Delay Insensitive)-style MSP430 micro-controller of TI (Texas Instruments) was designed as a case study.
n Research on AES Core for Smart Card Robust to Differential Power Analysis Technique, funded by the Ministry of Information and Communication (Currently, Ministry of Knowledge and Economy) of Korea, 2002. 7. – 2004. 6.
- Asynchronous circuits are known to be robust to attacks such as SPA (simple power attack) or DPA(differential power attack) to H/W cryptographic systems due to its lack of clock signals. In this project, DPA-immune asynchronous AES were studied and developed.
n Development of Asynchronous Design Technique for efficient IP integration in SOC, funded by Korea Research Foundation, 2002-2003
- In GALS (Globally Asynchronous and Locally Synchronous) environment, a clock-driven VLSI IP(Intellectual Property) is incorporated into that environment. The issues of synchronization, wrapper for local clock in GALS were addressed in this project.
n Verilog Parser Development Project, funded by IPEAN (Currently, System Centroid), 2002.10 – 2003. 10
- To equip a verilog parser for web-based commercial CAD tool, “Flowrian”, in which synthesis and simulation are performed in server-side and the results are transported to client-side via the Internet, we developed a verilog parser engine for front-end of the synthesis tool.
n SDL-C Translator Development Project, funded by ETRI, 2000. 3 -2001.2
n SDL Parser Development for H/W-S/W Co-Design Environment Project, funded by ETRI, 1999. 3-1999.8
- With related to the above two projects, we adopted SDL(Specification and Description Language) as a system-level specification language for H/W-S/W co-design environment. SDL is an ITU-T standard specification language by which behaviors of communication protocol, real-time system, etc are described.
Publications
Dissertation
n “A Study on Generation of Control Signal in High-Level Synthesis from SDL Specification”, Sang-Hoon Kwak, Master Thesis, Gwangju Institute of Science and Technology, Nov. 1999.
n “Optimization Methodology of Binary Adder Using Integer Linear Programming and Its Application to Multimedia System”, Sanghoon Kwak, Ph.D.Thesis, Gwangju Institute of Science and Technology, Dec. 2008.
International Journal Papers
1. “The Power-Delay Product Optimization of Heterogeneous Adder Using Integer Linear Programming”, Sanghoon Kwak, Jeong-Gun Lee, Jeong-A Lee, Dongsoo Har, Submitted to IEICE Trans. On Fundamentals of Electronics, Communications and Computer Sciences (Submitted)
2. “Exploration of Power-Delay Tradeoffs with Heterogeneous Adders by Integer Linear Programming”, Sanghoon Kwak, Eun-Gu Jung, Dongsoo Har, Jeong-gun Lee, Milos D. Ercegovac, Jeong-A Lee, Journal of Circuits, Systems and Computers (Accepted, to be published in Vol. 18, No. 4, Jun. 2009)
3. “Novel Hardware Architecture of Intra-Predictor Generator for H.264/AVC Codec”, Sanghoon Kwak, Jinwook Kim, Dongsoo Har, IEICE Trans. On Information and Systems, Vol. E91-D, No. 7, pp.2083-2086, Jul. 2008.
4. “Asynchronous Multiple-Issue On-Chip Bus with in-Order/Out-of-Order Completion”, Eun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Son Jhang, Jeong-a Lee, Dong-Soo Har, IEICE Trans. on Electronics, Vol.E88-C, pp. 2395-2399, Dec. 2005.
International Conference Papers
1. “Design of Asynchronous MSP430 Microprocessor Using Balsa Back-End Retargeting”, Sanghoon Kwak, Hyung-Woo Lee, Yousaf Zafar, Myeong-Hoon Oh, Dongsoo Har, In Proceedings of IEEE Vth Southern Conference on Programmable Logic (SPL’2009), pp. 223-228, Apr. 2009.
2. “Design of Heterogeneous Adders Based on Power-delay Tradeoffs”, Sanghoon Kwak, Dongsoo Har, Jeong-Gun Lee, Jeong-A Lee, In Proceedings of IEEE International Symposium on Embedded Computing (SEC’2008), pp. 223-226, Oct. 2008
3. “Fast Quarter-Pixel Motion Estimation by Adaptive Searching Point Selection”, Sanghoon Kwak, Hyunsup Shin, Dongsoo Har, In Proceeding of International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC'2007), pp. 797-798, 2007.
4. “Implementation of High-Performance Intra-Predictor In H.264”, Jinwook Kim, Eungu Jung, Eonpyo Hong, Sanghoon Kwak, Dongsoo Har, In Proceedings of IBERCHIP XII Workshop (IBERCHIP’07), pp. 343-344, 2007.
5. “High Performance Architecture for Intra Predictor in H.264”, Jinwook Kim, Eungu Jung, Sanghoon Kwak, and Dongsoo Har, In Proceedings of The Korea-Russia Joint-Workshop, pp. 149-152, Oct. 2006
6. “A Detection-Driven Watermarking Technique for VLSI IP Protection”, Sanghoon Kwak, Jeong-A Lee, Dongsoo Har, In Proceedings of International MultiConference of Engineers and Computer Scientists 2006 (IMEC’2006), pp. 149-152, Jun. 2006 (Best Paper Nominated)
7. “An Effective Scheduling Algorithm Targeting High Utilization of Reconfigurable Devices in Reconfigurable Co-synthesis System”, Jihan Park, Sanghoon Kwak, Fahad Ali Mujahid, Jeonga Lee, Dongsoo Har, In Proceedings of IBERCHIP XII Workshop (IBERCHIP’06), pp. 310-311, Mar. 2006
8. “Reconfigurable Co-synthesis System Architecture”, Ji-han Park, Sang-Hoon Kwak, Jeong-Gun Lee, Jeong-A Lee, and Dong-soo Har, In Proceedings of International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC'2005), pp. 445-446, 2005
9. "High Performance Asynchronous On-Chip Bus with Multiple Issue and Out-of-Order/In-Order Completion”, Eun-Gu Jung, Jeong-Gun Lee, Sang-Hoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har, In Proceedings of Proceedings of ACM Great Lakes symposium on VLSI (GLSVLSI '05), pp. 152-155, Apr. 2005.
10. “Generation of Control Signals in High-Level Synthesis from SDL Specification,” Sang-Hoon Kwak, Dong-Ik Lee, In Proceedings of International Technical Conference of Circuits/Systems, Computers and Communications (ITC-CSCC'2000), Vol. 1, pp. 410-413, Jul. 2000.
Domestic Journal Papers (Written in Korean)
1. “Automatic SDL to embedded C Code Generation Considering uC/OS-II OS Environment”, Sanghoon Kwak, Jeong-Gun Lee, Journal of KSCI, Vol. 13, No. 3, pp.45-55, May 2008
Domestic Conference Papers (Written in Korean)
1. “Synthesis of Area-Efficient Delay-Insensitive Asynchronous Circuit Using Balsa”, Sanghoon Kwak, Hyung-Woo Lee, Gyudong Choi, Myeong-Hoon Oh, Sungnam Kim, Sungwoon Kim, Dongsoo Har, In Proceedings of IEEK Fall Conference, Vol. 31, No. 2. pp. 989-990 , Nov. 2008.
2. "Synthesis of Asynchronous Circuits from C Language Using Syntax Directed Translation," Sang-Hoon Kwak, Jeong-Gun Lee and Dong-Ik Lee, In Proceedings of IEEK Summer Conference, pp. 353-356, Jun. 2002.
3. “Generation of C Code from SDL Specification Considering Real-Time Operating System”, S.-H. Kwak, D.-I. Lee, In Proceedings of KISS Fall Conference”, pp. 469-471, Oct. 2001.
Collaborators
Prof. Jeong-Gun Lee at Dept. of Info. & Comm., Hallym University (MPSoC, Asynchronous Circuits, etc)
Dr. Myeong-Hoon Oh at Server Platform Research Team, ETRI (Asynchronous Circuits, MVL, etc)
Links
Resources
l Prof. Sudeep Pasricha’s On-chip Communication Architecture Links
l Cambridge University’s NoC Research Group Page
Tools
l Orion
l Hotspot
l ARTS
l MPARM